1. l Field of the Invention
The present invention relates generally to methods for forming interconnect structures within integrated circuit devices. More particularly, the present invention relates to a method for forming a direct connection between an interconnect structure formed within an integrated circuit and the surface of an active semiconductor substrate region immediately adjoining that interconnect structure.
2. Description of the Prior Art
The overall performance or a semiconductor integrated circuit device chip is defined primarily by two factors. The first factor is the performance characteristics of the individual transistors and other circuit elements which are formed within and upon the semiconductor substrate from which the integrated circuit device chip is formed. The performance of these circuit elements is defined largely by the design parameters to which the circuit elements must be fabricated and the limitations of the fabrication tooling and processes used to achieve those design parameters.
The second factor which significantly affects semiconductor integrated circuit device chip performance is the characteristics of the conductors which are used to interconnect the circuit elements within the semiconductor integrated circuit device chip. In general the performance or the conductors deteriorates as: (1) they become longer in length, (2) they adjoin other conductors from which they may sustain parasitic effects, and (3) they terminate in highly resistive connections to contact regions of semiconductor integrated circuit device elements.
Thus, as the packing density and performance requirements for advanced generations of integrated circuit device chips increases, it is important to consider the performance requirements of both the individual circuit elements within the integrated circuit device chip and the methods by which the individual circuit elements are interconnected. Consideration of both of these factors will optimally assure the desired levels of overall chip performance.
Traditionally, interconnections between transistor devices and other circuit elements contained within semiconductor integrated circuit chips have been made through the use of patterned metallization connection lines defined upon the surface of the semiconductor substrate within which the integrated circuit elements are formed. The patterned metal lines are typically isolated from each other and separated from the semiconductor substrate by intermetallic and interlevel dielectric layers formed upon the semiconductor substrate from materials such as silicon oxide and silicon nitride. While these traditional interconnection methods have served well in providing adequate interconnections for traditional semiconductor integrated circuit device chips, they ten provide inadequate performance for advanced and evolving generations of integrated circuit device chips.
Thus, to the end of sustaining advances in semiconductor integrated circuit device chip performance, several novel interconnection technologies and materials have evolved which are directed towards enhancing the performance of conductive interconnections within semiconductor integrated circuit chips. These technologies and materials include: (1) the use of direct polysilicon interconnects with buried contacts to doped semiconductor device contact regions in order to limit parasitic losses due to longer interconnection schemes formed from metal lines, (2) the use of self-aligned contact technology for avoiding increased contact resistance due to mis-registration, and (3) the use of silicide barrier layers which reduce conductor contact resistance and metal penetration into semiconductor device and circuit element contact regions.
While all of the above technologies and materials are pertinent to the present invention, their application is best understood within the context of the use of interconnect structures within semiconductor integrated circuit device chips. Interconnect structures are typically formed upon the surface of an isolation region which separates active regions within an integrated circuit chip. Interconnects have several applications within semiconductor device technology. For example, they may be used to interconnect contact regions of adjoining integrated circuit device elements which are separated by the isolation region upon which the interconnect is formed. Alternatively, they may be used to bring to the surface of the isolation region a contact to an integrated circuit element which would otherwise be located to close to an adjoining contact.
The design and methods of fabrication of interconnect structures are known in the art. For example, Matsuoka, in U.S. Pat. No. 5,053,349 teaches a method for interconnecting semiconductor devices which includes forming a titanium silicide or tungsten metal bridge between the adjoining surfaces of a polysilicon interconnect and a source/drain electrode of a field effect transistor. In particular, the disclosure describes prior art problems which include: (1) the interdiffusion of dopants which occurs through direct contact between a doped polysilicon interconnect structure and an active semiconductor region of differing conductivity type, and (2) the formation of ditches within semiconductor substrates when polysilicon interconnects are formed upon those surfaces in the absence of an adequate etch stop barrier.
The structure disclosed by Matsuoka is shown in FIG. 1a. In FIG. 1a, a semiconductor substrate 10 has formed therein an active region defined by isolation regions 12a and 12b. Formed upon the active region is a polysilicon gate electrode 14a upon a gate oxide 13b. Formed partially upon the active region and partially upon the isolation region 12b is a polysilicon interconnect 14b upon a gate oxide 13c. The isolation region 12a, the gate electrode 14a and the interconnect 14b define a pair of source/drain electrodes 16a and 16b. Insulating layers 18a, 18b, 18c and 18d define silicon surfaces upon which are formed conductive layers 20a, 20b and 20c. The conductive layers are formed of either tungsten metal or titanium silicide. Conductive layer 20b provides a bridge between interconnect 14b and source/drain electrode 16b. Within this structure the source/drain electrodes 16a and 16b are formed prior to the insulating layers 18a, 18b, 18c and 18d.
Another example of an interconnect structure is disclosed by Wei, in U.S. Pat. No. 5,346,860. In comparison with Matsuoka, Wei discloses a multi-layer structure for forming a silicide interconnect between an active semiconductor substrate region and a conductor formed remotely upon an oxide isolation region adjoining the active semiconductor substrate region. Similar to the interconnect structure taught by Matsuoka, the interconnect structure disclosed by Wei is also directed to limiting outdiffusion of dopants from active semiconductor substrate regions upon which the interconnect is formed. In addition, the disclosure of Wei is also directed to forming an interconnect which consumes a limited amount of silicon from the surface of the silicon semiconductor substrate upon which the interconnect is formed.
The interconnect disclosed by Wei is shown in FIG. 1b. in FIG. 1b there is shown a semiconductor substrate 10 having an active region adjoining an isolation region 12. A polysilicon gate electrode 14a and a polysilicon conductor 14b are formed respectively upon remote locations of the active region and the isolation region 12. A source/drain electrode 16 is formed within the semiconductor substrate 10 between the polysilicon gate 14a and the isolation region 12. A metal layer 15 is formed on the surfaces of the polysilicon gate electrode 14a, the source/drain electrode 16, the isolation region 12 and the polysilicon conductor 14b. After a self-aligned silicidation process, the portion of the metal layer 15 which resides beneath structure 19 forms a silicide interconnect bridging the source/drain electrode 16 and the polysilicon conductor 14b. Structure 19 is formed from an oxide insulating layer 17 formed over an amorphous silicon layer 18.
Not disclosed are methods and materials which extend the prior art of interconnect structures having metal or metal silicide layers which bridge to active semiconductor substrate regions immediately adjoining those interconnect structures. Nor are there disclosed in the prior art alternate semiconductor process methodologies which: (1) are more compatible with the Lightly Doped Drain (LDD) type transistor formation process and conventional self-aligned silicidation processes, and (2) maintain the integrity of critical functions within semiconductor devices to which an interconnect is formed.